1. The Field of the Invention
The present invention relates to systems and methods for amplifying electrical signals. More specifically, the present invention relates to systems and methods for performing amplification by charge transfer.
2. The Prior State of the Art
There are many circuits and methods conventionally available for amplifying an electrical signal. One type of amplifier is called a charge transfer amplifier. Charge transfer amplifiers operate on the principle of capacitive charge sharing. Voltage amplification is achieved by transferring a specific amount of charge between appropriately sized capacitors through an active device.
FIG. 1 illustrates a charge transfer amplifier 100 that utilizes an nMOS transistor N1 to transfer charge between capacitors CT and CO. The operation of the nMOS charge transfer amplifier 100 will now be described in order to illustrate the basic principle of charge transfer amplification.
The nMOS charge transfer amplifier 100 operates in a cycle of three phases including a reset phase, a precharge phase, and an amplify phase. FIG. 2 is a signal timing diagram for two input signals S.sub.1 and S.sub.2 with respect to the cycle phase that the nMOS charge transfer amplifier 100 is operating in whether that phase be (a) the reset phase, (b) the precharge phase or (c) the amplify phase. The two input signals S.sub.1 and S.sub.2 control corresponding switches S1 and S2 of FIG. 1.
The cycle begins with the (a) reset phase in which the signal S.sub.1 is high indicating that the switch S1 is closed, and in which the signal S.sub.2 is low indicating that the switch S2 is open. Since the switch S1 is closed, the upper terminal of capacitor CT (i.e., node A) is discharged through the switch S1 to voltage Vss while the switch S2 is open thus isolating the nMOS transistor N1 as well as node B and the upper terminal of capacitor CO from the precharge voltage V.sub.PR thereby preventing static current flow through the nMOS transistor N1.
After the reset phase is the (b) precharge phase in which the signal S.sub.1 is low indicating that switch S1 is open, and in which the signal S.sub.2 is high indicating that the switch S2 is closed. Thus, the upper terminal of the capacitor CO (i.e., node B) is charged to the precharge voltage V.sub.PR. This precharge voltage V.sub.PR is high enough that current flows from node B to the capacitor CT (and node A) through the nMOS transistor N1. For example, if the precharge voltage V.sub.PR is at least equal to the input voltage V.sub.IN at the gate of the nMOS transistor N1, then the discharge continues until the voltage at the capacitor CT increases to be equal to the input voltage V.sub.IN minus the threshold voltage (hereinafter "V.sub.TN ") of the nMOS transistor N1. At that point, the nMOS transistor N1 enters the cutoff region and current flow to the capacitor C.sub.T substantially ceases. Thus, at the end of the precharge phase, the capacitor CO ideally has a voltage of V.sub.PR while the capacitor CT has a voltage of V.sub.PR -V.sub.TN.
After the precharge phase is the (c) amplify phase in which both signals S.sub.1 and S.sub.2 are low indicating that both switches S1 and S2 are open. During the amplify phase, an incrementally positive input voltage change .DELTA.V.sub.IN at the gate of the nMOS transistor N1 will cause the nMOS transistor N1 to turn on thereby allowing current to flow through the nMOS transistor N1 until the nMOS transistor is again cutoff. For small incrementally positive voltage changes .DELTA.V.sub.IN, the nMOS transistor N1 will cutoff when the voltage on upper terminal of the capacitor CT (i.e., node A) increases by the incrementally positive voltage change .DELTA.V.sub.IN. The amount of charge transferred to the capacitor CT in order to produce this effect is equal to the incrementally positive voltage change .DELTA.V.sub.IN times the capacitance C.sub.T of the capacitor CT.
Since the charge .DELTA.V.sub.IN.times.C.sub.T transferred to the capacitor CT came from node B through transistor N1, the charge .DELTA.V.sub.IN.times.C.sub.T was drawn from the capacitor CO. Thus, the voltage at the capacitor CO and the output voltage V.sub.OUT will change by .DELTA.V.sub.IN.times.(C.sub.T /C.sub.0). If the capacitance C.sub.T is greater than the capacitance C.sub.0, amplification occurs.
One advantage of the nMOS charge transfer amplifier 100 is that the voltage gain and power consumption may be controlled by setting the capacitance of the capacitors CO and CT as well as by setting the capacitance ratio C.sub.T /C.sub.0.
Another advantage of charge transfer amplifiers in general is that the circuit performance is generally unaffected by the absolute values of the supply voltage Vss and Vdd as long as these voltages permit proper biasing during the reset and precharge phases. In other words, charge transfer amplifiers have high supply voltage scalability in that no changes are needed for a charge transfer amplifier to operate using a wide range of supply voltages Vss and Vdd.
Although the nMOS charge transfer amplifier 100 has these advantages, there are at least two disadvantages to amplifying using the nMOS charge transfer amplifier 100.
First, amplification only occurs if the input gate voltage change .DELTA.V.sub.IN is positive. A negative gate voltage change .DELTA.V.sub.IN would only cause the nMOS transistor N1 to enter deeper into the cutoff region. Thus, charge transfer between node A and node B would be stifled thereby preventing amplification.
Second, leakage currents inherent in transistor N1 will alter the expected zero-bias (i.e., no input signal) conditions on capacitors CT and CO during the amplify phase. This leakage current may be caused by current undesirably leaking from the source/drain diffusion regions of the nMOS transistor N1 into the substrate in which they are formed. Leakage current may also be caused by current flowing between the source and drain terminals of the nMOS transistor N1 even though the nMOS transistor N1 is substantially cutoff. Either way, this leakage current effectively produces a voltage error V.sub.ERROR at the output terminal that introduces amplification error. The voltage error V.sub.ERROR becomes very large over time and is highly affected by temperature conditions. Instead of ideally producing a proportionally amplified output voltage V.sub.OUT according to the formula V.sub.OUT =.DELTA.V.sub.IN.times.(C.sub.T /C.sub.0), the amplifier would produce an output voltage V.sub.OUT with an error factor according to the formula V.sub.OUT =.DELTA.V.sub.IN.times.(C.sub.T /C.sub.0)-V.sub.ERROR.
FIG. 3 shows a conventional CMOS charge transfer amplifier 300 that substantially overcomes the above-described limitations of the nMOS charge transfer amplifier 100. The CMOS charge transfer amplifier 300 includes the nMOS charge transfer amplifier 100 described above. For clarity, the nMOS charge transfer amplifier 100 is shown in FIG. 3 as being enclosed by a dotted box. The CMOS charge transfer amplifier 300 also includes a partially overlapping pMOS charge transfer amplifier 301 which is shown in FIG. 3 enclosed by a dashed box for clarity. The pMOS charge transfer amplifier 301 shares the voltage input line 302, the voltage output line 303 and the precharge line 304 with the nMOS charge transfer amplifier 100. The pMOS charge transfer amplifier 301 is structured similar to the nMOS charge transfer amplifier 100 except that the pMOS charge transfer amplifier 301 uses a pMOS transistor P1 instead of an nMOS transistor N1 for transferring charge between capacitors. Also, node A' of the pMOS charge transfer amplifier 301 is reset to a high voltage Vdd instead of the low voltage Vss and is capacitively coupled to the high voltage Vdd instead of the low voltage Vss.
The general operation of the pMOS charge transfer amplifier 301 for negative input voltage changes .DELTA.V.sub.IN is similar to the operation of the nMOS charge transfer amplifier 100 for positive voltage changes .DELTA.V.sub.IN. Thus, the input signals S.sub.1 and S.sub.2 of FIG. 2 are used in the operation of the CMOS charge transfer amplifier 300. Due to the complementary nature of the nMOS charge transfer amplifier 100 and the pMOS charge transfer amplifier 301, the CMOS charge transfer amplifier 300 amplifies for both positive and negative input voltage changes .DELTA.V.sub.IN thereby overcoming one of the two described limitations of the nMOS charge transfer amplifier 100. Furthermore, the offset voltage V.sub.OFFSET may be minimized by sizing the nMOS transistor N1 and the pMOS transistor P1 so that the leakage currents match closely. While the match is never perfect or even predictable, the overall voltage error is usually lowered relative to the voltage error of the nMOS charge transfer amplifier 100 alone.
While the voltage error is improved by the addition of a complementary pMOS charge transfer amplifier 301 to the nMOS charge transfer amplifier 100, the voltage error is still too large to permit use with precision applications. This is due to the difficulty in sizing the transistors N1 and P1 to match leakage currents and due to the different rates of leakage current fluctuation in nMOS and pMOS transistors with changes in ambient temperature and sampling frequency. Recent constructions of the CMOS charge transfer amplifier 300 have shown voltage error of several millivolts depending on the ambient temperature and the clock speed.
As an additional disadvantage, the CMOS charge transfer amplifier 300 is single-ended and thus suffers from high common-mode noise. Common-mode noise is the amount of effect caused at the output terminal by the voltages at the input terminals changing together.
It would, therefore, represent an advancement in the art to create a charge transfer amplifier in which the offset voltage due to leakage current is reduced and in which common-mode rejection is increased. It would represent yet a further advancement in the art if such a configuration maintained the appeal of low power operation and accurate gain control in the presence of device parameter and temperature variations. It would represent yet a further advancement in the art if such a configuration maintained the appeal of high supply voltage scalability.